What’s I2C
I2C is a serial protocol used for a two-wire interface to connect low-speed devices such as microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces, and other similar peripherals in embedded systems. It is synchronous, multi-master, multi-slave, packet switching, single-ended, serial communication bus invented by Philips Semiconductors (now NXP Semiconductors) in 1982.
I²C only uses two bidirectional Open Drains (serial data (SDA) and serial clock (SCL)) and uses resistors to pull up the potential. I²C allows a considerable operating voltage range, but the typical voltage level is +3.3V or +5v.
The I²C reference design uses a 7-bit address space but reserves 16 addresses, so it can communicate with up to 112 nodes in a group of buses [a]. The common I²C bus has different modes: standard mode (100 kbit/s), low-speed mode (10 kbit/s), but the clock frequency can be allowed to drop to zero, which means that communication can be suspended. The new generation of I²C bus can communicate with more nodes (supporting 10-bit address space) at a faster rate: fast mode (400 kbit/s), fast mode plus (1 Mbit/s), high-speed mode (3.4 Mbit/s), ultra fast-mode (5 Mbit/s).
What is I²S?
I²S (Inter-IC Sound) is an electronic serial bus interface standard used for connecting digital audio devices together, this standard was first introduced by Philips Semiconductor in 1986. It is used to transfer PCM audio data between integrated circuits in electronic devices.
The I2S Hardware Interface:
1. Bit clock line
Formally called "Continuous Serial Clock (SCK)". Usually written as "bit clock (BCLK)".
That is, each bit of data corresponding to digital audio, SCLK has a pulse.
The frequency of SCLK = 2 × sampling frequency × number of sampling bits.
2. Word clock line
Formally known as "word selection (WS)". [Commonly referred to as "LRCLK" or "Frame Sync (FS)".
0 = left channel, 1 = right channel
3. At least one multiplexed data line
Formally called "Serial Data (SD)", but can be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, etc.
Timing diagram of I²S
